Low-power VLSI decoder architectures for LDPC codes
Proceedings of the 2002 international symposium on Low power electronics and design
Low cost LDPC decoder for DVB-S2
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Layered Decoding of Non-Layered LDPC Codes
DSD '06 Proceedings of the 9th EUROMICRO Conference on Digital System Design
Alternative Approximation of Check Node Algorithm for DVB-S2 LDPC Decoder
ICSNC '07 Proceedings of the Second International Conference on Systems and Networks Communications
Conflict resolution by matrix reordering for DVB-T2 LDPC decoders
GLOBECOM'09 Proceedings of the 28th IEEE conference on Global telecommunications
A novel LDPC decoder for DVB-S2 IP
Proceedings of the Conference on Design, Automation and Test in Europe
Approximate-min* constraint node updating for LDPC code decoding
MILCOM'03 Proceedings of the 2003 IEEE conference on Military communications - Volume I
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Good error-correcting codes based on very sparse matrices
IEEE Transactions on Information Theory
GPU-like on-chip system for decoding LDPC codes
ACM Transactions on Embedded Computing Systems (TECS)
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Layered decoding is known to provide efficient and high-throughput implementation of LDPC decoders. However, two main issues affect performance and area of practical implementations: quantization and memory. Quantization can strongly degrade performance and memory area can constitute up to 70% of the total area of the decoder implementation. This is the case of the DVB-S2,-T2 and -C2 decoders when considering long frames. This paper is then dedicated to the optimization of these decoders. We first focus on the reduction of the number of quantization bits and propose solutions based on the efficient saturation of the channel values, the extrinsic messages and the a posteriori probabilities (APP). We reduce from 6 to 5 the number of quantization bits for the channel and the extrinsic messages and from 8 to 6 the APPs, without introducing any performance loss. We then consider the optimization of the size of the extrinsic memory considering a multiple code rates decoder. The paper finally presents an optimized fixed-point architecture of a DVB-S2 layered decoder and its implementation on an FPGA device.