Parallel LDPC decoding on GPUs using a stream-based computing approach
Journal of Computer Science and Technology - Special section on trust and reputation management in future computing systmes and applications
Massively LDPC Decoding on Multicore Architectures
IEEE Transactions on Parallel and Distributed Systems
Approximate-min* constraint node updating for LDPC code decoding
MILCOM'03 Proceedings of the 2003 IEEE conference on Military communications - Volume I
Memory Access Optimized Implementation of Cyclic and Quasi-Cyclic LDPC Codes on a GPGPU
Journal of Signal Processing Systems
A massively parallel implementation of QC-LDPC decoder on GPU
SASP '11 Proceedings of the 2011 IEEE 9th Symposium on Application Specific Processors
Architecture and Finite Precision Optimization for Layered LDPC Decoders
Journal of Signal Processing Systems
A low power multi-rate decoder hardware for IEEE 802.11n LDPC codes
Microprocessors & Microsystems
Factor graphs and the sum-product algorithm
IEEE Transactions on Information Theory
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Rapid prototyping is an important step in the development and the verification of computationally demanding tasks of digital communication systems, such as Forward Error Correction (FEC) decoding. The goal is to replace time-consuming simulations based on abstract models of the system with real-time experiments under real-world conditions. GPU-like architecture is a promising approach to fully exploit the potential of FPGA-based acceleration platforms. In this article, an application-specific GPU-like architecture and a complete compilation framework for decoding LDPC codes are proposed. The interest in an application-specific GPU in comparison with current GPUs is detailed. Finally, real-time experimentations demonstrate the potential of the GPU-like decoder to investigate both algorithmic and architectural issues.