Low cost LDPC decoder for DVB-S2
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
ASAP '06 Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors
Low complexity LDPC code decoders for next generation standards
Proceedings of the conference on Design, automation and test in Europe
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hardware efficient decoding of LDPC codes using partial-min algorithms
IEEE Transactions on Consumer Electronics
A 1-Gb/s flexible LDPC decoder supporting multiple code rates and block lengths
IEEE Transactions on Consumer Electronics
GPU-like on-chip system for decoding LDPC codes
ACM Transactions on Embedded Computing Systems (TECS)
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In this paper, we present a low power multi-rate decoder hardware for low density parity check (LDPC) codes used in IEEE 802.11n wireless Local Area Network standard and we propose two novel techniques, sub-matrix reordering and differential shifting, for reducing the power consumption of a LDPC decoder hardware. The proposed hardware is a hybrid LDPC decoder and it implements layered min-sum decoding algorithm. The LDPC decoder hardware is implemented in Verilog HDL and it is verified to work correctly for all 12 block length and code rate combinations specified in the standard. We applied glitch reduction, sub-matrix reordering and differential shifting techniques to our multi-rate LDPC decoder hardware, and they reduced its power consumption on a Xilinx Virtex II FPGA by 25.93% on the average with a maximum reduction of 32.68% achieved for block length 648 and code rate 5/6. These techniques do not affect the bit error rate of a LDPC decoder hardware.