Flexible LDPC decoder design for multigigabit-per-second applications
IEEE Transactions on Circuits and Systems Part I: Regular Papers
A low power multi-rate decoder hardware for IEEE 802.11n LDPC codes
Microprocessors & Microsystems
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This paper propose a new flexible low-density parity-check (LDPC) decoding architecture that can be dynamically reconfigured according to a parity-check matrix which changes as code rate or block length varies. Since the LDPC codes are adopted in standards such as DVB-S2, IEEE 802.1 In and IEEE 802.16e and each standard allows various code rates and block lengths, an LDPC decoder architecture that could support multiple code rates and code block lengths is needed. The proposed architecture employs Benes network to implement configurable interconnection network. In the proposed architecture the number of levels and the delay of the interconnection network is reduced by using broadcasting technique which transmits reduced messages to save the complexity of the interconnection network. The number of processing units in the proposed partially parallel architecture is determined by investigating the relation between hardware complexity and throughput. By applying pipelining to the processing units, decoding throughput is increased. To verify the proposed architecture, a flexible LDPC decoder is implemented using a 0.18 mum CMOS process. The decoder occupies an area of 16.261 mm and runs correctly at the frequency of 212 MHz resulting in 1 Gbps decoding throughput.