Probabilistic reasoning in intelligent systems: networks of plausible inference
Probabilistic reasoning in intelligent systems: networks of plausible inference
Nonuniformly quantized min-sum decoder architecture for low-density parity-check codes
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Low-complexity high-speed decoder design for quasi-cyclic LDPC codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multi-Gb/s LDPC code design and implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multi-Gb/s LDPC code design and implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Good error-correcting codes based on very sparse matrices
IEEE Transactions on Information Theory
A 1-Gb/s flexible LDPC decoder supporting multiple code rates and block lengths
IEEE Transactions on Consumer Electronics
VLSI implementation of a high-throughput soft-bit-flipping decoder for geometric LDPC codes
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special issue on ISCAS 2009
An area efficient LDPC decoder using a reduced complexity min-sum algorithm
Integration, the VLSI Journal
Flexible LDPC decoder architectures
VLSI Design - Special issue on Flexible Radio Design: Trends and Challenges in Digital Baseband Implementation
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Low-density parity-check (LDPC) codes are one of the most promising error-correcting codes approaching Shannon capacity and have been adopted in many applications. However, the efficient implementation of high-throughput LDPC decoders adaptable for various channel conditions still remains challenging. In this paper, a low-complexity reconfigurable VLSI architecture for high-speed LDPC decoders is presented. Shift-LDPC codes are incorporated within the design and have shown not only comparable decoding performance to computer-generated random codes but also high hardware efficiency in high-speed applications. The single-minimum Min-Sum decoding scheme and the nonuniform quantization scheme are explored to reduce the complexity of computing core and the memory requirement. The well-known Benes network is employed to construct the configurable permutation network to support multiple shift-LDPC codes with various code parameters. The ASIC implementation results of an (8192, 7168) (4, 32)-regular shift-LDPC decoder demonstrate a maximum decoding throughput of 3.6 Gbits/s at 16 iterations, which outperforms the state-of-the-art design for high-speed flexible LDPC decoders by many times with even less hardware.