Semi-Parallel Reconfigurable Architectures for Real-Time LDPC Decoding
ITCC '04 Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04) Volume 2 - Volume 2
A Flexible Hardware Encoder for Low-Density Parity-Check Codes
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A Synthesizable IP Core for DVB-S2 LDPC Code Decoding
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
Partially-Parallel LDPC Decoder Based on High-Efficiency Message-Passing Algorithm
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Efficient encoding of low-density parity-check codes
IEEE Transactions on Information Theory
Quasicyclic low-density parity-check codes from circulant permutation matrices
IEEE Transactions on Information Theory
Configurable LDPC Decoder Architectures for Regular and Irregular Codes
Journal of Signal Processing Systems
Regular non-binary quasi-cyclic LDPC codes for high-rate applications
Proceedings of the 2009 International Conference on Wireless Communications and Mobile Computing: Connecting the World Wirelessly
Geometrically-structured maximum-girth LDPC block and convolutional codes
IEEE Journal on Selected Areas in Communications - Special issue on capaciyy approaching codes
High-throughput layered decoder implementation for quasi-cyclic LDPC codes
IEEE Journal on Selected Areas in Communications - Special issue on capaciyy approaching codes
Efficient shuffle network architecture and application for WiMAX LDPC decoders
IEEE Transactions on Circuits and Systems II: Express Briefs
Decoder design for RS-based LDPC codes
IEEE Transactions on Circuits and Systems II: Express Briefs
Seed graph expansion for construction of structured LDPC codes
ISWCS'09 Proceedings of the 6th international conference on Symposium on Wireless Communication Systems
A lattice-based systematic recursive construction of quasi-cyclic LDPC codes
IEEE Transactions on Communications
FPGA-based low-complexity high-throughput tri-mode decoder for quasi-cyclic LDPC codes
Allerton'09 Proceedings of the 47th annual Allerton conference on Communication, control, and computing
Min-sum decoder architectures with reduced word length for LDPC codes
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Flexible LDPC decoder design for multigigabit-per-second applications
IEEE Transactions on Circuits and Systems Part I: Regular Papers
A Split-Decoding Message Passing Algorithm for Low Density Parity Check Decoders
Journal of Signal Processing Systems
Quasi-cyclic LDPC codes: an algebraic construction, rank analysis, and codes on Latin squares
IEEE Transactions on Communications
A Flexible LDPC/Turbo Decoder Architecture
Journal of Signal Processing Systems
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Improved Sliced Message Passing Architecture for High Throughput Decoding of LDPC Codes
Journal of Signal Processing Systems
Modified Shuffled Based Architecture for High-Throughput Decoding of LDPC Codes
Journal of Signal Processing Systems
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This paper studies low-complexity high-speed decoder architectures for quasi-cyclic low density parity check (QC-LDPC) codes. Algorithmic transformation and architectural level optimization are incorporated to reduce the critical path. Enhanced partially parallel decoding architectures are proposed to linearly increase the throughput of conventional partially parallel decoders through introducing a small percentage of extra hardware. Based on the proposed architectures, a (8176, 7154) Euclidian geometry-based QC-LDPC code decoder is implemented on Xilinx field programmable gate array (FPGA) Virtex-II 6000, where an efficient nonuniform quantization scheme is employed to reduce the size of memories storing soft messages. FPGA implementation results show that the proposed decoder can achieve a maximum (source data) decoding throughput of 172 Mb/s at 15 iterations.