Reconfigurable Shuffle Network Design in LDPC Decoders
ASAP '06 Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors
Low-complexity high-speed decoder design for quasi-cyclic LDPC codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of a multimode QC-LDPC decoder based on shift-routing network
IEEE Transactions on Circuits and Systems II: Express Briefs
A Split-Decoding Message Passing Algorithm for Low Density Parity Check Decoders
Journal of Signal Processing Systems
A multimode shuffled iterative decoder architecture for high-rate RS-LDPC codes
IEEE Transactions on Circuits and Systems Part I: Regular Papers
QSN: a simple circular-shift network for reconfigurable quasi-cyclic LDPC decoders
IEEE Transactions on Circuits and Systems II: Express Briefs
Flexible LDPC decoder architectures
VLSI Design - Special issue on Flexible Radio Design: Trends and Challenges in Digital Baseband Implementation
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In this brief, a new algorithm that can efficiently generate all the control signals for the shuffle network used in flexible low-density parity-check (LDPC) decoders is proposed. Employing the proposed algorithm, the hardware complexity of the controller of shuffle networks using the Benes network structure can be significantly reduced. In addition, a low-complexity reconfigurable shuffle network architecture for flexible LDPC decoders is developed. Both the Benes network and the controller can be tailored to fit specific applications. Consequently, an efficient shuffle network for WiMAX LDPC decoders is presented. Synthesis results demonstrate that with the SMIC 0.18-µm complementary metal-oxide-semiconductor process, the total gate count of the proposed shuffle network is only 16 000. The area saving is between 26.6% and 71.1% compared to related works in the literature.