Low-power VLSI decoder architectures for LDPC codes
Proceedings of the 2002 international symposium on Low power electronics and design
Rapid Design and Analysis of Communication Systems Using the BEE Hardware Emulation Environment
RSP '03 Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP'03)
Semi-Parallel Reconfigurable Architectures for Real-Time LDPC Decoding
ITCC '04 Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04) Volume 2 - Volume 2
A Synthesizable IP Core for DVB-S2 LDPC Code Decoding
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
ASAP '06 Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors
High-Throughput Multi-Rate Decoding of Structured Low-Density Parity-Check Codes
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Low-complexity high-speed decoder design for quasi-cyclic LDPC codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient encoding of low-density parity-check codes
IEEE Transactions on Information Theory
Analysis of sum-product decoding of low-density parity-check codes using a Gaussian approximation
IEEE Transactions on Information Theory
QSN: a simple circular-shift network for reconfigurable quasi-cyclic LDPC decoders
IEEE Transactions on Circuits and Systems II: Express Briefs
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Low Density Parity Check (LDPC) codes are one of the best error correcting codes that enable the future generations of wireless devices to achieve higher data rates with excellent quality of service. This paper presents two novel flexible decoder architectures. The first one supports (3,6) regular codes of rate 1/2 that can be used for different block lengths. The second decoder is more general and supports both regular and irregular LDPC codes with twelve combinations of code lengths 驴驴648,1296,1944-bits and code rates-1/2,2/3,3/4,5/6- based on the IEEE 802.11n standard. All codes correspond to a block-structured parity check matrix, in which the sub-blocks are either a shifted identity matrix or a zero matrix. Prototype architectures for both LDPC decoders have been implemented and tested on a Xilinx field programmable gate array.