BEE2: A High-End Reconfigurable Computing System
IEEE Design & Test
An integrated debugging environment for reprogrammble hardware systems
Proceedings of the sixth international symposium on Automated analysis-driven debugging
A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH
ACM Transactions on Embedded Computing Systems (TECS)
Configurable LDPC Decoder Architectures for Regular and Irregular Codes
Journal of Signal Processing Systems
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Efficient in-system RTL verification and debugging using FPGAs (abstract only)
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
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This paper describes the early analysis and estimationfeatures currently implemented in the Berkeley EmulationEngine (BEE) system. BEE is an integrated rapid prototypingand design environment for communication and digitalsignal processing (DSP) systems, consisting of four multi-FPGA based processing units, each capable of emulating 10 million ASIC (Application Specific Integrated Circuits)equivalent gates at an overall system clock rate up to 60MHz. This translates to over 600 billion 16-bit additions(operations) per second on one unit. An integrated softwaredesign flow enables the users to specify the design using adata-flow diagram, then automatically generates both theFPGA implementation for real-time rapid prototyping anda cycle-accurate, bit-true, and functionally equivalent ASICimplementation. For system-level design, the BEE hardwareand software support rapid design turn-around and early performance analysis, without full synthesis or hardwaremapping, from the high-level design entry. A case study detailing a turbo-decoder explains how the processingcapability of the emulator can be utilized to verify a design using one billion input vectors with a speed-up factorexceeding 106 over equivalent software simulationmethods.