Rapid Design and Analysis of Communication Systems Using the BEE Hardware Emulation Environment
RSP '03 Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP'03)
Intel® atom™ processor core made FPGA-synthesizable
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Intel nehalem processor core made FPGA synthesizable
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
gNOSIS: A Board-Level Debugging and Verification Tool
RECONFIG '10 Proceedings of the 2010 International Conference on Reconfigurable Computing and FPGAs
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
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FPGAs have become indispensible in processor design, bring-up and debug. Traditionally FPGAs have been used in prototyping, allowing end-users to emulate functionality of a specific component of a processor. However, as the complexity of processors grows, another aspect of processor design, RTL verification, has become a prime target for acceleration using FPGAs. Software-only RTL simulation and verification tools are no longer sufficient for many verification tasks as they often incur long execution time penalties. Software simulation time for a basic Linux kernel bring-up on a BlueGene/Q [1] processor, with 16 user PowerPC A2 cores, for example, could easily exceed several years. An important feature of RTL verification acceleration using FPGAs is its fast debugging capabilities. The ability to quickly and accurately pinpoint the location of an anomaly in an RTL source is highly desirable. This paper proposes efficient in-system debugging techniques on FPGAs for RTL verification. We show how a network of over 45 Virtex 5 LX330 FPGAs can be efficiently used to read out state information of the BlueGene/Q processor. We also demonstrate how the new in-system debugging technique is 250x faster than comparable methods.