FPGA prototyping of a RISC processor core for embedded applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Rapid Design and Analysis of Communication Systems Using the BEE Hardware Emulation Environment
RSP '03 Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP'03)
Intel® atom™ processor core made FPGA-synthesizable
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
FPGA prototyping of a multi-million gate System-on-Chip (SoC) design for wireless USB applications
Proceedings of the 2009 International Conference on Wireless Communications and Mobile Computing: Connecting the World Wirelessly
Intel nehalem processor core made FPGA synthesizable
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
SoC HW/SW verification and validation
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Efficient in-system RTL verification and debugging using FPGAs (abstract only)
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Towards simulator-like observability for FPGAs: a virtual overlay network for trace-buffers
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Co-simulation framework of SystemC SoC virtual prototype and custom logic (abstract only)
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Iterative routing algorithm of Inter-FPGA signals for Multi-FPGA prototyping platform
ARC'13 Proceedings of the 9th international conference on Reconfigurable Computing: architectures, tools, and applications
Modeling, validation, and co-design of IBM Blue Gene/Q: tools and examples
IBM Journal of Research and Development
Fast full-system execution-driven performance simulator for blue gene/q
Euro-Par'13 Proceedings of the 19th international conference on Parallel Processing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Frequency optimization objective during system prototyping on multi-FPGA platform
International Journal of Reconfigurable Computing
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Software based tools for simulation are not keeping up with the demands for increased chip and system design complexity. In this paper, we describe a cycle-accurate and cycle-reproducible large-scale FPGA platform that is designed from the ground up to accelerate logic verification of the Bluegene/Q compute node ASIC, a multi-processor SOC implemented in IBM's 45 nm SOI CMOS technology. This paper discusses the challenges for constructing such large-scale FPGA platforms, including design partitioning, clocking & synchronization, and debugging support, as well as our approach for addressing these challenges without sacrificing cycle accuracy and cycle reproducibility. The resulting fullchip simulation of the Bluegene/Q compute node ASIC runs at a simulated processor clock speed of 4 MHz, over 100,000 times faster than the logic level software simulation of the same design. The vast increase in simulation speed provides a new capability in the design cycle that proved to be instrumental in logic verification as well as early software development and performance validation for Bluegene/Q.