PathFinder: a negotiation-based performance-driven router for FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
SMAP: heterogeneous technology mapping for area reduction in FPGAs with embedded memory arrays
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Instrumenting Bitstreams for Debugging FPGA Circuits
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Algorithms for state restoration and trace-signal selection for data acquisition in silicon debug
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
LEMON - an Open Source C++ Graph Template Library
Electronic Notes in Theoretical Computer Science (ENTCS)
Improved Abstractions and Turnaround Time for FPGA Design Validation and Debug
FPL '11 Proceedings of the 2011 21st International Conference on Field Programmable Logic and Applications
Speculative Debug Insertion for FPGAs
FPL '11 Proceedings of the 2011 21st International Conference on Field Programmable Logic and Applications
The VTR project: architecture and CAD for FPGAs from verilog to routing
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Reducing the cost of floating-point mantissa alignment and normalization in FPGAs
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Towards simulator-like observability for FPGAs: a virtual overlay network for trace-buffers
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Escaping the Academic Sandbox: Realizing VPR Circuits on Xilinx Devices
FCCM '13 Proceedings of the 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines
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FPGA technology is commonly used to prototype new digital designs before entering fabrication. Whilst these physical prototypes can operate many orders of magnitude faster than through a logic simulator, a fundamental limitation is their lack of on-chip visibility when debugging. To counter this, trace-buffer-based instrumentation can be installed into the prototype, allowing designers to capture a predetermined window of signal data during live operation for offline analysis. However, instead of requiring the designer to recompile their entire circuit every time the window is modified, this article proposes that an overlay network is constructed using only spare FPGA routing multiplexers to connect all circuit signals through to the trace instruments. Thus, during debugging, designers would only need to reconfigure this network instead of finding a new place-and-route solution. Furthermore, we describe how this network can deliver signals to both the trigger and trace units of these instruments, which are implemented simultaneously using dual-port RAMs. Our results show that new network configurations connecting any subset of signals to 80--90% of the available RAM capacity can be computed in less than 70 seconds, for a 100,000 LUT circuit, as many times as necessary. Our tool—QuickTrace—is available for download.