Design for Test: For Digital Integrated Circuits
Design for Test: For Digital Integrated Circuits
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
JHDL - An HDL for Reconfigurable Systems
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
A CAD Suite for High-Performance FPGA Design
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A Reconfigurable Computing Architecture for Microsensors
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Reconfigurable architectures for general-purpose computing
Reconfigurable architectures for general-purpose computing
Design for Testability A Survey
IEEE Transactions on Computers
Multitasking Hardware on the SLAAC1-V Reconfigurable Computing System
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Long-term on-chip verification of systems with logical events scattered in time
Microprocessors & Microsystems
Towards simulator-like observability for FPGAs: a virtual overlay network for trace-buffers
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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This paper describes a structured technique for providing full observability and controllability for functionally debugging FPGA designs in hardware, capabilities which are currently not available otherwise. Similar in concept to flip-flop scan chains for VLSI, our design-level scan technique includes all FPGA flip-flops and RAMs in a serial scan chain using FPGA logic rather than transistor logic. This paper describes the general procedure for modifying designs with design-level scan chains and provides the results of adding scan to several designs, both large and small. We observed an average FPGA resource overhead of 84% for full scan and only 60% when we augmented existing FPGA capabilities with scan to provide complete observability and controllability in hardware.