The PowerPC architecture: a specification for a new family of RISC processors
The PowerPC architecture: a specification for a new family of RISC processors
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Automated target recognition on SPLASH 2
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Field Programmable Gate Array Based Radar Front-End Digital Signal Processing
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A CAD Suite for High-Performance FPGA Design
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Reconfigurable Processing: The Solution to Low-Power Programmable DSP
ICASSP '97 Proceedings of the 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '97) -Volume 1 - Volume 1
Flexible image acquisition using reconfigurable hardware
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Reconfigurable architectures for general-purpose computing
Reconfigurable architectures for general-purpose computing
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Applications of adaptive computing systems for signal processing challenges
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
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An adaptive amplification operation has been designed and tested in configurable hardware for a computationally intensive object recognition system. This configurable system provides over forty-one times the throughput of an industry-standard embedded processor by exploiting the bandwidth of internal block memories and parallelism within the algorithm. Operating at less than one half the power of the programmable processor, the configurable approach performs the computation with 90 times less energy. The improvements in both performance and power are obtained by customizing the datapath, memory interfaces, and control to the amplification algorithm.