Test Routines Based on Symbolic Logical Statements
Journal of the ACM (JACM)
The concurrent simulation of nearly identical digital networks
DAC '73 Proceedings of the 10th Design Automation Workshop
Test generation costs analysis and projections
DAC '80 Proceedings of the 17th Design Automation Conference
Fault-test analysis techniques based on logic simulation
DAC '72 Proceedings of the 9th Design Automation Workshop
TEGAS2—anatomy of a general purpose TEST GENERATION AND SIMULATION system for digital logic
DAC '72 Proceedings of the 9th Design Automation Workshop
Test generation systems in Japan
DAC '75 Proceedings of the 12th Design Automation Conference
A new look at test generation and verification
DAC '77 Proceedings of the 14th Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Automatic checking of logic design structures For compliance with testability ground rules
DAC '77 Proceedings of the 14th Design Automation Conference
Test generation for large logic networks
DAC '77 Proceedings of the 14th Design Automation Conference
DAC '77 Proceedings of the 14th Design Automation Conference
DAC '77 Proceedings of the 14th Design Automation Conference
Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic
IEEE Transactions on Computers
On Modifying Logic Networks to Improve Their Diagnosability
IEEE Transactions on Computers
The Boolean Difference and Multiple Fault Analysis
IEEE Transactions on Computers
Detection oF Pattern-Sensitive Faults in Random-Access Memories
IEEE Transactions on Computers
Multiple Fault Detection for Combinational Logic Circuits
IEEE Transactions on Computers
Fault Location in a Semiconductor Random-Access Memory Unit
IEEE Transactions on Computers
A Deductive Method for Simulating Faults in Logic Circuits
IEEE Transactions on Computers
Fault Masking in Combinational Logic Circuits
IEEE Transactions on Computers
The Probability of a Correct Output from a Combinational Circuit
IEEE Transactions on Computers
Analysis of Logic Circuits with Faults Using Input Signal Probabilities
IEEE Transactions on Computers
On Minimally Testable Logic Networks
IEEE Transactions on Computers
Optimal Test Generation in Combinational Networks by Pseudo-Boolean Programming
IEEE Transactions on Computers
A Module-Level Testing Approach for Combinational Networks
IEEE Transactions on Computers
Transition Count Testing of Combinational Logic Circuits
IEEE Transactions on Computers
The Error Latency of a Fault in a Sequential Digital Circuit
IEEE Transactions on Computers
A Heuristic Algorithm for the Testing of Asynchronous Circuits
IEEE Transactions on Computers
The Weighted Random Test-Pattern Generator
IEEE Transactions on Computers
An Algorithm for the Generation of Test Sets for Combinational Logic Networks
IEEE Transactions on Computers
Properties of Faults and Criticalities of Values under Tests for Combinational Networks
IEEE Transactions on Computers
Analyzing Errors with the Boolean Difference
IEEE Transactions on Computers
IEEE Transactions on Computers
Fault Detecting Test Sets for Reed-Muller Canonic Networks
IEEE Transactions on Computers
Cause-Effect Analysis for Multiple Fault Detection in Combinational Networks
IEEE Transactions on Computers
Derivation of Minimum Test Sets for Unate Logical Circuits
IEEE Transactions on Computers
Fault Equivalence in Combinational Logic Networks
IEEE Transactions on Computers
Comparison of Parallel and Deductive Fault Simulation Methods
IEEE Transactions on Computers
Optimal and Near-Optimal Checking Experiments for Output Faults in Sequential Machines
IEEE Transactions on Computers
Easily Testable Realizations ror Logic Functions
IEEE Transactions on Computers
Fault Folding for Irredundant and Redundant Combinational Circuits
IEEE Transactions on Computers
Functional Partitioning and Simulation of Digital Circuits
IEEE Transactions on Computers
Modeling and Digital Simulation for Design Verification and Diagnosis
IEEE Transactions on Computers
A Nand Model ror Fault Diagnosis in Combinational Logic Networks
IEEE Transactions on Computers
Derivation of optimum test sequencies for sequential machines
SWCT '64 Proceedings of the 1964 Proceedings of the Fifth Annual Symposium on Switching Circuit Theory and Logical Design
A model and implementation of a universal time delay simulator for large digital nets
AFIPS '70 (Spring) Proceedings of the May 5-7, 1970, spring joint computer conference
A New Representation for Faults in Combinational Digital Circuits
IEEE Transactions on Computers
Diagnosis of automata failures: a calculus and a method
IBM Journal of Research and Development
On the necessity to examine D-chains in diagnostic test generation-an example
IBM Journal of Research and Development
Hazard detection in combinational and sequential switching circuits
IBM Journal of Research and Development
Accumulator Compression Testing
IEEE Transactions on Computers - The MIT Press scientific computation series
Testable Design of Single-Output Sequential Machines Using Checking Experiments
IEEE Transactions on Computers
Test Schedules for VLSI Circuits Having Built-In Test Hardware
IEEE Transactions on Computers - The MIT Press scientific computation series
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
IBM Journal of Research and Development
Advanced microprocessor test strategy and methodology
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
PATEGE: an automatic DC parametric test generation system for series gated ECL circuits
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Heuristic-Driven Test Case Selection from Formal Specifications. A Case Study
FME '02 Proceedings of the International Symposium of Formal Methods Europe on Formal Methods - Getting IT Right
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
A C-testable modified Booth's array multiplier
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
A Novel BIST Architecture With Built-in Self Check
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
A practical approach to instruction-based test generation for functional modules of VLSI processors
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
13.1 A Study on the Utility of Using Expected Quality Level as a Design for Testability Metric
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Sequential Network Design Using Extra Inputs for Fault Detection
IEEE Transactions on Computers
The Design of Easily Testable VLSI Array Multipliers
IEEE Transactions on Computers
A Self-Testing Group-Parity Prediction Checker and Its Use for Built-In Testing
IEEE Transactions on Computers
Exhaustive Test Pattern Generation with Constant Weight Vectors
IEEE Transactions on Computers
Synthesis of reversible sequential elements
ACM Journal on Emerging Technologies in Computing Systems (JETC)
AFIPS '82 Proceedings of the June 7-10, 1982, national computer conference
Multi-agent-based integrated framework for intra-class testing of object-oriented software
Applied Soft Computing
On minimizing memory in systolic arrays for the dynamic time warping algorithm
Integration, the VLSI Journal
Security considerations in the design and implementation of a new DES chip
EUROCRYPT'87 Proceedings of the 6th annual international conference on Theory and application of cryptographic techniques
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
microSPARCTM: a case-study of scan based debug
ITC'94 Proceedings of the 1994 international conference on Test
Multi-frequency, multi-phase scan chain
ITC'94 Proceedings of the 1994 international conference on Test
Do you practice safe test? what we found out about your habits
ITC'94 Proceedings of the 1994 international conference on Test
Concurrent control of multiple BIT structures
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Design for testability of mixed signal integrated circuits
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Designs for dlagnosablllty and reliability in VLSI systems
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
A New PLA Design for Universal Testability
IEEE Transactions on Computers
Automatic test pattern generation for asynchronous networks
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Higher certainty of error coverage by output data modification
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Design of test pattern generators for built-in test
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Automated synthesis of pseudo-exhaustive test generator in VLSI BIST design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper discusses the basics of design for testability. A short review of testing is given along with some reasons why one should test. The different techniques of design for testability are discussed in detail. These include techniques which can be applied to today's technologies and techniques which have been recently introduced and will soon appear in new designs.