Multiple-Fault Detection and Location in Fan-Out Free Combinational Circuits
IEEE Transactions on Computers
Multiple Fault Detection in Combinational Circuits: Algorithms and Computational Results
IEEE Transactions on Computers
Fault Testing and Diagnosis in Combinational Digital Circuits
IEEE Transactions on Computers
Analyzing Errors with the Boolean Difference
IEEE Transactions on Computers
Minimal Fault Tests for Combinational Networks
IEEE Transactions on Computers
An Efficient Algorithm for Generating Complete Test Sets for Combinational Logic Circuits
IEEE Transactions on Computers
Cause-Effect Analysis for Multiple Fault Detection in Combinational Networks
IEEE Transactions on Computers
Fault Folding for Irredundant and Redundant Combinational Circuits
IEEE Transactions on Computers
Detection of Multiple Faults in Combinational Logic Networks
IEEE Transactions on Computers
A New Representation for Faults in Combinational Digital Circuits
IEEE Transactions on Computers
Design for Testability A Survey
IEEE Transactions on Computers
IEEE Transactions on Computers
A Remark on the Nonminimality of Certain Multiple Fault Detection Algorithms
IEEE Transactions on Computers
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An algorithm for generating test sets to detect all the multiple stuck-at-faults in combinational logic circuits is presented. This algorithm generates a test set using a set of functions, called representative functions, which consists of much fewer functions than all possible multiple stuck-at fault functions, but is sufficient for test generation. Two different methods of finding such a set of representative functions are presented. The test sets derived from the set of representative functions obtained by the first method will be smaller than that by the second method, but the second method is much simpler than the first especially for highly redundant circuits. Nevertheless, the complexity of this algorithm using the first method is about the same as that of Bossen and Hong's algorithm which is the simplest existing algorithm under the multiple stuck-at fault assumption, and yet the number of tests in a test set generated will always be smaller for redundant circuits and the same for irredundant circuits as that generated by Bossen and Hong's algorithm for irredundant circuits.