Spectral Signature Testing of Multiple Stuck-at Faults in Irredundant Combinational Networks
IEEE Transactions on Computers
Design for Testability A Survey
IEEE Transactions on Computers
Multiple Fault Detection for Combinational Logic Circuits
IEEE Transactions on Computers
A Tree Representation of Combinational Networks
IEEE Transactions on Computers
Comments on "Minimal Fault Tests for Combinational Networks"
IEEE Transactions on Computers
Multiple Fault Detection in Combinational Circuits: Algorithms and Computational Results
IEEE Transactions on Computers
Generic Fault Characterizations for Table Look-Up Coverage Bounding
IEEE Transactions on Computers
Fault Masking in Combinational Logic Circuits
IEEE Transactions on Computers
A Method for Obtaining SPOOF's
IEEE Transactions on Computers
Multiple Fault Detection in Programmable Logic Arrays
IEEE Transactions on Computers
A Remark on the Nonminimality of Certain Multiple Fault Detection Algorithms
IEEE Transactions on Computers
Minimal Fault Tests for Redundant Combinational Networks
IEEE Transactions on Computers
Complete Test Sets for Logic Functions
IEEE Transactions on Computers
On the Existence of Combinational Logic Circuits Exhibiting Multiple Redundancy
IEEE Transactions on Computers
Identification of Multiple Stuck-Type Faults in Combinational Networks
IEEE Transactions on Computers
A New Representation for Faults in Combinational Digital Circuits
IEEE Transactions on Computers
Fault Table Computation on GPUs
Journal of Electronic Testing: Theory and Applications
LSI logic testing: an overview
IEEE Transactions on Computers
| Hi-index | 15.03 |
The important problem of generating test patterns to detect multiple faults has received little attention, mainly due to their computational complexity. The theoretical results of this paper show that near minimal tests for multiple faults can be generated with complexity of computation comparable to that of single faults.