Cause-Effect Analysis for Multiple Fault Detection in Combinational Networks
IEEE Transactions on Computers
Fault Equivalence in Combinational Logic Networks
IEEE Transactions on Computers
A Nand Model ror Fault Diagnosis in Combinational Logic Networks
IEEE Transactions on Computers
Spectral Signature Testing of Multiple Stuck-at Faults in Irredundant Combinational Networks
IEEE Transactions on Computers
Advanced microprocessor test strategy and methodology
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
Fanout fault analysis for digital logic circuits
ATS '95 Proceedings of the 4th Asian Test Symposium
Design of Totally Fault Locatable Combinational Networks
IEEE Transactions on Computers
Design for Testability A Survey
IEEE Transactions on Computers
Multiple Fault Detection for Combinational Logic Circuits
IEEE Transactions on Computers
Generic Fault Characterizations for Table Look-Up Coverage Bounding
IEEE Transactions on Computers
Reliability Modeling of Compensating Module Failures in Majority Voted Redundancy
IEEE Transactions on Computers
The Probability of a Correct Output from a Combinational Circuit
IEEE Transactions on Computers
A Rollback Interval for Networks with an Imperfect Self-Checking Property
IEEE Transactions on Computers
Transition Count Testing of Combinational Logic Circuits
IEEE Transactions on Computers
Identification of Equivalent Faults in Logic Networks
IEEE Transactions on Computers
Multiple Fault Testing of Large Circuits by Single Fault Test Sets
IEEE Transactions on Computers
Identification of Multiple Stuck-Type Faults in Combinational Networks
IEEE Transactions on Computers
An analysis of the multiple fault detection capabilities of single stuck-at fault test sets
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
LSI logic testing: an overview
IEEE Transactions on Computers
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A new representation for faults in combinational digital circuits is presented. Faults that are inherently indistinguishable are identified and combined into classes that form a geometric structure that effectively subdivides the original circuit into fan-out-free segments. This fan-out-free characteristic allows a simplified analysis of multiple fault conditions. For certain circuits, including all two-level single-output circuits, it is shown that the detection of all single faults implies the detection of all multiple faults. The behavior of any circuit under fault conditions is represented in terms of the classes of indistinguishable faults. This results in a description of the faulty circuit by means of Boolean equations that are readily manipulated for the purpose of fault simulation or test generation. A connection graph interpretation of this fault representation is discussed. Heuristic methods for the selection of efficient tests without extensive computation are derived from these connection graphs.