Timesharing system design concepts (McGraw-Hill computer science series)
Timesharing system design concepts (McGraw-Hill computer science series)
A Nand Model ror Fault Diagnosis in Combinational Logic Networks
IEEE Transactions on Computers
A New Representation for Faults in Combinational Digital Circuits
IEEE Transactions on Computers
Accumulator Compression Testing
IEEE Transactions on Computers - The MIT Press scientific computation series
Testable Design of Single-Output Sequential Machines Using Checking Experiments
IEEE Transactions on Computers
An Alternative to Scan Design Methods for Sequential Machines
IEEE Transactions on Computers - The MIT Press scientific computation series
A unified view of test compression methods
IEEE Transactions on Computers
Syndrome signature in output compaction for VLSI BIST
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Design for Testability A Survey
IEEE Transactions on Computers
Generation of Optimal Transition Count Tests
IEEE Transactions on Computers
On the Impossible Class of Faulty Functions in Logic Networks Under Short Circuit Faults
IEEE Transactions on Computers
Efficiency of Random Compact Testing
IEEE Transactions on Computers
Syndrome-Testable Design of Combinational Circuits
IEEE Transactions on Computers
Measures of the Effectiveness of Fault Signature Analysis
IEEE Transactions on Computers
Fault-Tolerant Computing: A Introduction
IEEE Transactions on Computers
Testing by Feedback Shift Register
IEEE Transactions on Computers
An Analysis of the Use of Rademacher-Walsh Spectrum in Compact Testing
IEEE Transactions on Computers
Synchronous Sequential Machines: A Modular and Testable Design
IEEE Transactions on Computers
International Journal of Computer Mathematics
| Hi-index | 15.02 |
Logic circuits are usually tested by applying a sequence of input patterns S to the circuit under test and comparing the observed response sequence R bit by bit to the expected response Ro. The transition count (TC) of R, denoted c(R), is the number of times the signals forming R change value. In TC testing c(R) is recorded rather than R. A fault is detected if the observed TC c(R) differs from the correct TC c(Ro). This paper presents a formal analysis of TC testing. It is shown that the degree of detectability and distinguishability of faults obtainable by TC testing is less than that obtainable by conventional testing. t is argued that the TC tests should be constructed to maximize or minimize c(Ro). General methods are presented for constructing complete TC tests to detect both single and multiple stuck-line faults in combinational circuits. Optimal or near-optimal test sequences are derived for one-and two-level circuits. The use of TC testing for fault location is examined, and it is concluded that TC tests are relatively inefficient for this purpose.