Complete test-set generation for bridging faults in combinational-logic circuits
Information Sciences: an International Journal
Arithmetic Spectrum Applied to Fault Detection for Combinational Networks
IEEE Transactions on Computers
Translation of the Problem of Complete Test Set Generation to Pseudo-Boolean Programming
IEEE Transactions on Computers
Syndrome-Testable Design of Combinational Circuits
IEEE Transactions on Computers
Transition Count Testing of Combinational Logic Circuits
IEEE Transactions on Computers
Analyzing Errors with the Boolean Difference
IEEE Transactions on Computers
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This paper reports on the development of a novel scheme as an alternative to Susskind's method [A.K. Susskind, Testing by verifying Walsh coefficients, Proceedings of the 11th Annual Symposium on fault-tolerant computing, June 1981, pp. 206-208.] for detection of struck-at faults in combinational logic circuits. The main idea in the present scheme is to extend an existing design of the combinational network under test in minterm format by some logic checking the correctness of all input-output mappings by computing only one novel parameter after cycling through all 2n input combinations of a circuit with n inputs. Thus the present scheme uses 2n n-bit input patterns once to a circuit while Susskind's method uses twice that many. So it provides substantially less work than that needed in Susskind's method. Furthermore, the tester needed to implement the present scheme is a simplified version of that needed in Susskind's method.