A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Probabilistic Treatment of General Combinational Networks
IEEE Transactions on Computers
Transition Count Testing of Combinational Logic Circuits
IEEE Transactions on Computers
A Practical Approach to Fault Detection in Combinational Networks
IEEE Transactions on Computers
On Realizations of Boolean Functions Requiring a Minimal or Near-Minimal Number of Tests
IEEE Transactions on Computers
Detection of Multiple Faults in Combinational Logic Networks
IEEE Transactions on Computers
Accumulator Compression Testing
IEEE Transactions on Computers - The MIT Press scientific computation series
Testable Design of Single-Output Sequential Machines Using Checking Experiments
IEEE Transactions on Computers
An Alternative to Scan Design Methods for Sequential Machines
IEEE Transactions on Computers - The MIT Press scientific computation series
Spectral Signature Testing of Multiple Stuck-at Faults in Irredundant Combinational Networks
IEEE Transactions on Computers
Signature Analysis for Multiple-Output Circuits
IEEE Transactions on Computers
A unified view of test compression methods
IEEE Transactions on Computers
Testing programmable logic arrays by sum of syndromes
IEEE Transactions on Computers
Aliasing errors in linear automata used as multiple-input signature analyzers
IBM Journal of Research and Development
An improved output compaction technique for built-in self-test in VLSI circuits
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Syndrome signature in output compaction for VLSI BIST
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
New BIST Techniques for Universal and Robust Testing of CMOS Stuck-Open Faults
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Exact probabilistic analysis of error detection for parity checkers
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Testing by Verifying Walsh Coefficients
IEEE Transactions on Computers
On the Impossible Class of Faulty Functions in Logic Networks Under Short Circuit Faults
IEEE Transactions on Computers
Built-In Testing of One-Dimensional Unilateral Iterative Arrays
IEEE Transactions on Computers
Syndrome-Testability Can be Achieved by Circuit Modification
IEEE Transactions on Computers
Syndrome-Testing of " Syndrome-Untestable" Combinational Circuits
IEEE Transactions on Computers
An Analysis of the Use of Rademacher-Walsh Spectrum in Compact Testing
IEEE Transactions on Computers
IEEE Transactions on Computers
IEEE Transactions on Computers
Spectral Fault Signatures for Internally Unate Combinational Networks
IEEE Transactions on Computers
The Weighted Syndrome Sums Approach to VLSI Testing
IEEE Transactions on Computers
Good Controllability and Observability Do Not Guarantee Good Testability
IEEE Transactions on Computers
International Journal of Computer Mathematics
Random-pattern coverage enhancement and diagnosis for LSSD logic self-test
IBM Journal of Research and Development
Universal syndrome-testable design of programmable logic arrays
Integration, the VLSI Journal
On multiple fault coverage and aliasing probability measures
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
IEEE Transactions on Computers
Spectral Fault Signatures for Single Stuck-At Faults in Combinational Networks
IEEE Transactions on Computers
Higher certainty of error coverage by output data modification
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Post-silicon bug diagnosis with inconsistent executions
Proceedings of the International Conference on Computer-Aided Design
| Hi-index | 15.03 |
Classical testing of combinational circuits requires a list of the fault-free response of the circuit to the test set. For most practical circuits implemented today the large storage requirement for such a list makes such a test procedure very expensive. Moreover, the computational cost to generate the test set increases exponentially with the circuit size.