Test Length for Pseudorandom Testing
IEEE Transactions on Computers
Fault Propagation Through Embedded Multiport Memories
IEEE Transactions on Computers
A method for generating weighted random test pattern
IBM Journal of Research and Development
IBM Journal of Research and Development
IBM Journal of Research and Development
A Probabilistic Power Prediction Tool for the Xilinx 4000-Series FPGA
IPDPS '00 Proceedings of the 15 IPDPS 2000 Workshops on Parallel and Distributed Processing
Accurate Power Estimation of Logic Structures Based on Timed Boolean Functions
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
An almost full-scan BIST solution-higher fault coverage and shorter test application time
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Techniques for Estimation of Design Diversity for Combinational Logic Circuits
DSN '01 Proceedings of the 2001 International Conference on Dependable Systems and Networks (formerly: FTCS)
A symbolic simulation approach in resolving signals' correlation
SS '96 Proceedings of the 29th Annual Simulation Symposium (SS '96)
Low-Power Driven Logic Synthesis Using Accurate Power Estimation Technique
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Deriving Signal Constraints to Accelerate Sequential Test Generation
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
A Fault-Independent Transitive Closure Algorithm for Redundancy Identification
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Power Reduction in Test-Per-Scan BIST
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
Probabilistic Bottom-Up RTL Power Estimation
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
GlitchMap: an FPGA technology mapper for low power considering glitches
Proceedings of the 44th annual Design Automation Conference
Probabilistic transfer matrices in symbolic reliability analysis of logic circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Boolean Network Probabilities and Network Design
IEEE Transactions on Computers
Sequential Circuit Output Probabilities From Regular Expressions
IEEE Transactions on Computers
The Probability of a Correct Output from a Combinational Circuit
IEEE Transactions on Computers
Analysis of Logic Circuits with Faults Using Input Signal Probabilities
IEEE Transactions on Computers
A Rollback Interval for Networks with an Imperfect Self-Checking Property
IEEE Transactions on Computers
Syndrome-Testable Design of Combinational Circuits
IEEE Transactions on Computers
On Monte Carlo Testing of Logic Tree Networks
IEEE Transactions on Computers
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
A routing approach to reduce glitches in low power FPGAs
Proceedings of the 2009 international symposium on Physical design
Novel probabilistic combinational equivalence checking
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Logic synthesis for reducing leakage power consumption under workload uncertainty
ICC'08 Proceedings of the 12th WSEAS international conference on Circuits
Computation of signal output probability for Boolean functions represented by OBDD
Computers & Mathematics with Applications
Optimal periodic testing policy for circuit with self-testing
Computers & Mathematics with Applications
A routing approach to reduce glitches in low power FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Stochastic computational models for accurate reliability evaluation of logic circuits
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Computation error analysis in digital signal processing systems with overscaled supply voltage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Soft error modeling and remediation techniques in ASIC designs
Microelectronics Journal
RALF: reliability analysis for logic faults: an exact algorithm and its applications
Proceedings of the Conference on Design, Automation and Test in Europe
Dynamic power estimation for deep submicron circuits with process variation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
IEEE Transactions on Computers
Random testing for stuck-at storage cells in an embedded memory
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Sufficient testing in a self-testing environment
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Applications of testability analysis: from ATPG to critical delay path tracing
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Cascaded Bayesian inferencing for switching activity estimation with correlated inputs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Integration, the VLSI Journal
Mitigation of soft errors in SRAM-based FPGAs using CAD tools
Computers and Electrical Engineering
A theoretical probabilistic simulation framework for dynamic power estimation
Proceedings of the International Conference on Computer-Aided Design
A method for switching activity analysis of VHDL-RTL combinatorial circuits
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
M-IVC: Applying multiple input vectors to co-optimize aging and leakage
Microelectronics Journal
Scalable sampling methodology for logic simulation: reduced-ordered Monte Carlo
Proceedings of the International Conference on Computer-Aided Design
An analytical method for reliability aware instruction set extension
The Journal of Supercomputing
| Hi-index | 15.01 |
In this correspondence two methods are given for calculating the probability that the output of a general combinational network is 1 given the probabilities for each input being 1. We define the notions of the probability of a signal and signal independence. Then several proofs are given to show the relationship between Boolean operations and algebraic operations upon probabilities. As a result of these, two simple algorithms are presented for calculating output probabilities. An example of the usefulness of these results is given with respect to the generation of tests for the purpose of fault detection.