A new model for computation of probabilistic testability in combinational circuits
Integration, the VLSI Journal
Introduction to algorithms
A formal non-heuristic ATPG approach
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
FIRE: a fault-independent combinational redundancy identification algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Neural Net and Boolean Satisfiability Models of Logic Circuits
IEEE Design & Test
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Redundancy Identification Using Transitive Closure
ATS '96 Proceedings of the 5th Asian Test Symposium
A New Transitive Closure Algorithm with Application to Redundancy Identification
DELTA '02 Proceedings of the The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02)
Static logic implication with application to redundancy identification
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
Probabilistic Treatment of General Combinational Networks
IEEE Transactions on Computers
Diagnosis of automata failures: a calculus and a method
IBM Journal of Research and Development
Diagnostic and Detection Fault Collapsing for Multiple Output Circuits
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
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We present a fault-independent redundancyidentification algorithm. The controllabilities and observabilitiesare defined as Boolean variables and representedon an implication graph. A major enhancementover previously published results is that we include alldirect and partial implications, as well as node fixation.The transitive closure, whose computation now requiresa new algorithm, provides many redundant faults in asingle-pass analysis. Because of these improvements,we obtain better performance than all previous fault-independentmethods at execution speeds that are muchfaster than any exhaustive ATPG. For example, in thes9234 circuit more than half of the redundant faults arefound in just 14 seconds on a Sparc 5. All 34 redundantfaults of c6288 are found in one pass. Besides, our singlepass procedure can classify faults according to the causesof their redundancy. The weakness of our method, as weillustrate by examples, lies in the lack of a formulationfor the observabilities of fanout stems.