FIRE: a fault-independent combinational redundancy identification algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test Counting: A Tool for VLSI Testing
IEEE Design & Test
Advanced Fault Collapsing (Logic Circuits Testing)
IEEE Design & Test
On the Equivalence of Fanout-Point Faults
IEEE Transactions on Computers
An Efficient Algorithm for Sequential Circuit Test Generation
IEEE Transactions on Computers
Diagnostic Fault Equivalence Identification Using Redundancy Information and Structural Analysis
Proceedings of the IEEE International Test Conference on Test and Design Validity
Looking for Functional Fault Equivalence
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Measured performance of a programmed implementation of the subscripted D-Algorithm
DAC '83 Proceedings of the 20th Design Automation Conference
A Fault-Independent Transitive Closure Algorithm for Redundancy Identification
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
A New Algorithm for Global Fault Collapsing into Equivalence and Dominance Sets
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Fault Equivalence Identification Using Redundancy Information and Static and Dynamic Extraction
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Testing of Digital Systems
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Using Contrapositive Law in an Implication Graph to Identify Logic Redundancies
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Evaluation of Collapsing Methods for Fault Diagnosis
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Multiple-fault diagnosis based on single-fault activation and single-output observation
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Improved diagnosis using enhanced fault dominance
Integration, the VLSI Journal
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We discuss fault equivalence and dominance relations for multiple output combinational circuits. The conventional definition for equivalence says that "Two faults are equivalent if and only if the corresponding faulty circuits have identical output functions". This definition, which is based on indistinguishability of the faults, is extended for multiple output circuits as "Two faults of a Boolean circuit are equivalent if and only if the pair of the output functions is identical at each output of the circuit". This is termed as diagnostic equivalence in this paper. "If all tests that detect a fault also detect another fault, not necessarily on the same output, then the two faults are called detection equivalent". Two detection equivalent faults need not be indistinguishable. The definitions for fault dominance follow on similar lines. A novel algorithm based on redundancy identification has been proposed to find the equivalence and dominance collapsed sets based on diagnostic and detection collapsing. Applying the algorithm to a 4-bit ALU would collapse the total fault set of 502 faults to 253 and 155, respectively, according to diagnostic equivalence and dominance. The collapsed sets have 234 and 92 faults, respectively, for detection equivalence and dominance. In comparison, the traditional structural equivalence and dominance collapsing results in 301 and 248 faults, respectively. Finally, we use library-based functional collapsing in a hierarchical system and find that smaller fault sets are obtained with an order of magnitude reduction in CPU time for very large circuits.