On diagnosis of pattern-dependent delay faults
Proceedings of the 37th Annual Design Automation Conference
Failure Diagnosis of Structured VLSI
IEEE Design & Test
Delay-Fault Diagnosis by Critical-Path Tracing
IEEE Design & Test
Modeling the Unmodelable: Algorithmic Fault Diagnosis
IEEE Design & Test
Poirot: Applications of a Logic Fault Diagnosis Tool
IEEE Design & Test
A diagnostic test generation procedure for synchronous sequential circuits based on test elimination
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Critical path tracing - an alternative to fault simulation
DAC '83 Proceedings of the 20th Design Automation Conference
Exclusive Test and its Applications to Fault Diagnosis
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Diagnostic Test Pattern Generation for Sequential Circuits
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Fault Distinguishing Pattern Generation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Multiplets, Models, and the Search for Meaning: Improving Per-Test Fault Diagnosis
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Testing of Digital Systems
Z-Sets and Z-Detections: Circuit Characteristics that Simplify Fault Diagnosis
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Design diagnosis using Boolean satisfiability
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Diagnostic and Detection Fault Collapsing for Multiple Output Circuits
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Effective TARO Pattern Generation
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Accurate Diagnosis of Multiple Faults
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Diagnosing arbitrary defects in logic designs using single location at a time (SLAT)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing-aware multiple-delay-fault diagnosis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Diagnostic Test Set Minimization and Full-Response Fault Dictionary
Journal of Electronic Testing: Theory and Applications
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In this paper, we propose a new circuit transformation technique in conjunction with the use of a special diagnostic test pattern, named SO-SLAT pattern, to achieve higher multiple-fault diagnosis resolutions. For a given list of candidate faults, which could be stuck-at, transition, bridging, or other faults, we generate a set of SO-SLAT patterns, each of which attempts to activate only one fault in the list and propagate its effects to only one observation point. Observing the responses to SO-SLAT patterns helps more precisely identify fault candidates. The method can also tolerate most of the timing hazards for more accurate diagnosis of failures caused by timing faults. The experimental results demonstrate the effectiveness of the proposed method for diagnosing multiple faults.