A diagnostic test generation procedure for synchronous sequential circuits based on test elimination

  • Authors:
  • Irith Pomeranz;Sudhakar M. Reddy

  • Affiliations:
  • -;-

  • Venue:
  • ITC '98 Proceedings of the 1998 IEEE International Test Conference
  • Year:
  • 1998

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Abstract

We propose a procedure for generating test sequences fordiagnosis of synchronous sequential circuits based onstuck-at faults. The test generation procedure avoids theconventional fault-oriented test generation by observingthat a sequence to distinguish two faults can be obtainedfrom a sequence that detects both of the faults (such as atest sequence for fault detection) by changing thesequence so as to "undetect" one of the faults. To achievethis goal, the proposed procedure eliminates parts of a testsequence for fault detection so as to render some of thefaults undetected. The faults that are detected by theresulting sequence are distinguished from the faults leftundetected by the sequence based on pass/fail informa-tion. A pass/fail dictionary suitable for diagnosis with theresulting test sequences is also proposed. Alternatively, aconventional dictionary can be used, and the proposedprocedure can be used to change the time units or outputswhere faults are detected, in order to distinguish them. Wepresent experimental results to demonstrate the levels ofresolution that can be obtained by the proposed procedurewith the proposed pass/fail dictionary, and the number ofsequences required for this purpose.