POPL '87 Proceedings of the 14th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Algorithms for solving Boolean satisfiability in combinational circuits
DATE '99 Proceedings of the conference on Design, automation and test in Europe
On using satisfiability-based pruning techniques in covering algorithms
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Interval Constraint Logic Programming
Selected Papers from Constraint Programming: Basics and Trends
A diagnostic test generation procedure for synchronous sequential circuits based on test elimination
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Diagnostic Test Pattern Generation for Sequential Circuits
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
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A number of diagnostic and optimisation problems in Electronics Computer Aided Design have usually been handled either by specific tools or by mapping them into a general problem solver (e.g. a propositional Boolean SAT tool). This approach, however, requires models with substantial duplication of digital circuits. In Constraint Logic Programming, the use of extra values in the digital signals (other than the usual 0/1) was proposed to reflect their dependency on some faulty gate. In this paper we present an extension of this modelling approach, using set variables to denote dependency of the signals on sets of faults, to model different circuits problems. We then show the importance of propagating constraints on sets cardinality, by comparing Cardinal, a set constraint solver that we implemented, with a simpler version that propagates these constraints similarly to Conjunto, a widely available set constraint solver. Results show speed ups of Cardinal of about two orders of magnitude, on a set of diagnostic problems.