The Multiple Observation Time Test Strategy
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Algorithms for approximate FSM traversal
DAC '93 Proceedings of the 30th international Design Automation Conference
On improving fault diagnosis for synchronous sequential circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Rapid diagnostic fault simulation of stuck-at faults in sequential circuits using compact lists
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Identification of unsettable flip-flops for partial scan and faster ATPG
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Classification of Faults in Synchronous Sequential Circuits
IEEE Transactions on Computers
Diagnostic Fault Equivalence Identification Using Redundancy Information and Structural Analysis
Proceedings of the IEEE International Test Conference on Test and Design Validity
GARDA: a diagnostic ATPG for large synchronous sequential circuits
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Characterization and Implicit Identification of Sequential Indistinguishability
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Identifying sequentially untestable faults using illegal states
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Diagnosis oriented test pattern generation
EURO-DAC '90 Proceedings of the conference on European design automation
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Dynamic fault collapsing and diagnostic test pattern generation for sequential circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Modeling the Unmodelable: Algorithmic Fault Diagnosis
IEEE Design & Test
Modelling Digital Circuits Problems with Set Constraints
CL '00 Proceedings of the First International Conference on Computational Logic
A diagnostic test generation procedure for synchronous sequential circuits based on test elimination
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Fault Distinguishing Pattern Generation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Diagnostic Test Generation for Sequential Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A Technique for Identifying RTL and Gate-Level Correspondences
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Journal of Electronic Testing: Theory and Applications
Accurate Diagnosis of Multiple Faults
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Multiple-fault diagnosis based on single-fault activation and single-output observation
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Electronic Notes in Theoretical Computer Science (ENTCS)
Journal of Electronic Testing: Theory and Applications
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A method to perform diagnostic test generation in sequential circuits by modifying a conventional test generator is presented. The method utilizes circuit netlist modification along with a forced value at a primary input in the modified circuit. Techniques to reduce the computational effort for diagnostic test pattern generation in sequential circuits are also presented. Speeding up the diagnostic ATPG process is achieved by the identification of states that are impossible to justify with three-valued logic.