Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG

Authors:
Andreas Veneris;Robert Chang;Magdy S. Abadir;Sep Seyedi
Affiliations:
Department of Electrical and Computer Engineering and Department of Electrical and Computer Science, University of Toronto, Toronto, Canada M5S 3G4;Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada M5S 3G4;Freescale Semiconductor, Inc., Austin, USA 78729;Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada M5S 3G4
Venue:
Journal of Electronic Testing: Theory and Applications
Year:
2005

Citing 10
Cited 1

Perturb and simplify: multi-level boolean network optimizer

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Sequential Circuit Design Using Synthesis and Optimization

ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Finding Good Counter-Examples to Aid Design Verification

MEMOCODE '03 Proceedings of the First ACM and IEEE International Conference on Formal Methods and Models for Co-Design
Diagnostic Test Pattern Generation for Sequential Circuits

VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
20.2 New Techniques for Deterministic Test Pattern Generation

VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Implication and Evaluation Techniques for Proving Fault Equivalence

VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
A New Algorithm for Global Fault Collapsing into Equivalence and Dominance Sets

ITC '02 Proceedings of the 2002 IEEE International Test Conference
Fault Equivalence Identification Using Redundancy Information and Static and Dynamic Extraction

VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Testing of Digital Systems

Testing of Digital Systems
Design rewiring using ATPG

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Gradual diagnostic test generation and observation point insertion based on the structural distance between indistinguished fault pairs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

In today's complex and challenging VLSI design process, multiple logic errors may occur due to the human factor and bugs in CAD tools. The designer often faces the challenge of correcting an erroneous design implementation. This study describes a simulation-based ...