Introduction to algorithms
DFT Strategy for Intel Microprocessors
Proceedings of the IEEE International Test Conference on Test and Design Validity
Pentium® Pro Processor Design for Test and Debug
Proceedings of the IEEE International Test Conference
A diagnostic test generation procedure for synchronous sequential circuits based on test elimination
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm
Proceedings of the IEEE International Test Conference 2001
Debug methodology for the McKinley processor
Proceedings of the IEEE International Test Conference 2001
GARDA: a diagnostic ATPG for large synchronous sequential circuits
EDTC '95 Proceedings of the 1995 European conference on Design and Test
POIROT1: A Logic Fault Diagnosis Tool and Its Applications
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Fault Tuples in Diagnosis of Deep-Submicron Circuits
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Multiple Fault Diagnosis Using n-Detection Tests
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Journal of Electronic Testing: Theory and Applications
Z-DFD: DESIGN-FOR-DIAGNOSABILITY BASED ON THE CONCEPT OF Z-DETECTION
ITC '04 Proceedings of the International Test Conference on International Test Conference
Panel Synopsis - Diagnosis Meets Physical Failure Analysis: How Long Can We Succeed?
ITC '04 Proceedings of the International Test Conference on International Test Conference
Panel 9 - Diagnostics vs. Failure Analysis
ITC '04 Proceedings of the International Test Conference on International Test Conference
Adaptive Debug and Diagnosis without Fault Dictionaries
ETS '07 Proceedings of the 12th IEEE European Test Symposium
Multiple defect diagnosis using no assumptions on failing pattern characteristics
Proceedings of the 45th annual Design Automation Conference
Precise failure localization using automated layout analysis of diagnosis candidates
Proceedings of the 45th annual Design Automation Conference
Enhancing Transition Fault Model for Delay Defect Diagnosis
ATS '08 Proceedings of the 2008 17th Asian Test Symposium
Output-Dependent Diagnostic Test Generation
VLSID '10 Proceedings of the 2010 23rd International Conference on VLSI Design
DFT '10 Proceedings of the 2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The size of a diagnostic test set is significantly larger than the size of a fault detection test set. As a result, fault detection test sets may be used for initial defect diagnosis, and diagnostic tests may be added as needed to narrow down a set of candidate defect sites. Between a fault detection test set and a full diagnostic test set there is a large range of test sets that can be used for improved (initial) diagnosis. This paper describes a diagnostic test generation process that produces such a range of test sets. The process is based on a ranking of the indistinguished fault pairs according to the importance of distinguishing them. The ranking is based on the structural distance between faults. This allows failure analysis to explore fewer and more localized areas of the circuit as the size of the diagnostic test set is increased. This paper also discusses the insertion of observation points to distinguish fault pairs that remain indistinguished by a diagnostic test set. Observation point insertion uses the ranked list of indistinguished fault pairs to ensure that a limited number of observation points will address the fault pairs that are the most important to distinguish.