IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Debugging faulty devices is an undesirable but necessary task for yield improvement and design debug at first silicon. If there are no defects in the entire production process, devices are shipped without screening. Of course, production requires testing to reject faulty devices; therefore debug - or elimination of sources causing defects - is an important task for yield improvement. On the other hand, when the first silicon of a new design shows functional violations or a very low yield, debug is a necessary task that should be completed as soon as possible to avoid the losses caused by delayed time to market and idling of expensive resources. Debug should cover all processes that potentially cause errors - almost the whole product flow from design to final test. Except for pure design errors, all debugging requires Failure Analysis that identifies the sources of the defects that cause the failures of faulty devices. Finally, hypothetical sources are confirmed by simulations, temporary fixes, or permanent fixes. The main objective of this panel is to discuss the effectiveness of failure analysis in future silicon debugging.