A deductive technique for diagnosis of bridging faults
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Test set compaction algorithms for combinational circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
A Heuristic Measure to Maximize Detected Faults per Test
Journal of Electronic Testing: Theory and Applications
On the Use of Fully Specified Initial States for Testing of Synchronous Sequential Circuits
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Static Test Compaction for Scan-Based Designs to Reduce Test Application Time
Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98
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An approach to test compaction for scan circuits that enhances at-speed testing
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On identifying don't care inputs of test patterns for combinational circuits
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Compact two-pattern test set generation for combinational and full scan circuits
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Accumulator based deterministic BIST
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits
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VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
On Static Test Compaction and Test Pattern Ordering for Scan Designs
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Aliasing-Free Space and Time Compactions with Limited Overhead
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
STAR-ATPG: A High Speed Test Pattern Generator for Large Scan Designs
ITC '99 Proceedings of the 1999 IEEE International Test Conference
The Effects of Test Compaction on Fault Diagnosis
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Test vector decomposition-based static compaction algorithms for combinational circuits
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On test data volume reduction for multiple scan chain designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuits
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Journal of Electronic Testing: Theory and Applications
Dynamic test compaction for a random test generation procedure with input cube avoidance
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IEICE - Transactions on Information and Systems
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents new cost-effective heuristics for the generation of minimal test sets. Both dynamic techniques, which are introduced into the test generation process, and a static technique, which is applied to already generated test sets, are used. The dynamic compaction techniques maximize the number of faults that a new test vector detects out of the yet-undetected faults as well as out of the already-detected ones. Thus, they reduce the number of tests and allow tests generated earlier in the test generation process to be dropped. The static compaction technique replaces N test vectors by M