An algorithm for diagnosing two-line bridging faults in combinational circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
Diagnosis of realistic bridging faults with single stuck-at information
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
E-PROOFS: a CMOS bridging fault simulator
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Beyond the Byzantine Generals: Unexpected Behaviour and Bridging Fault Diagnosis
Proceedings of the IEEE International Test Conference on Test and Design Validity
Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Poirot: Applications of a Logic Fault Diagnosis Tool
IEEE Design & Test
A new path-oriented effect-cause methodology to diagnose delay failures
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Multiple Design Error Diagnosis and Correction in Digital VLSI Circuits
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Path-Delay Fault Diagnosis in Non-Scan Sequential Circuits with At-Speed Test Application
ITC '00 Proceedings of the 2000 IEEE International Test Conference
POIROT1: A Logic Fault Diagnosis Tool and Its Applications
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Incremental Design Debugging in a Logic Synthesis Environment
Journal of Electronic Testing: Theory and Applications
Multiple defect diagnosis using no assumptions on failing pattern characteristics
Proceedings of the 45th annual Design Automation Conference
Precise failure localization using automated layout analysis of diagnosis candidates
Proceedings of the 45th annual Design Automation Conference
Layout-based defect-driven diagnosis for intracell bridging defects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Diagnosis of integrated circuits with multiple defects of arbitrary characteristics
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
Automated data analysis solutions to silicon debug
Proceedings of the Conference on Design, Automation and Test in Europe
Deterministic test for the reproduction and detection of board-level functional failures
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Extraction error modeling and automated model debugging in high-performance custom designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automating data analysis and acquisition setup in a silicon debug environment
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A deductive technique is presented that uses voltage testing for the diagnosis of single bridging faults between two gate input or output lines and is applicable to combinational or full-scan sequential circuits. For defects in this class of faults the method is accurate by construction while making no assumptions about the logic-level wired-AND/OR behavior. A path-trace procedure starting from failing outputs deduces potential lines associated with the bridge and eliminates certain faults. The information obtained from the path-trace from failing outputs is combined using an intersection graph to make further deductions. The intersection graph implicitly represents all candidate faults, thereby obviating the need to enumerate faults and hence allowing the exploration of the space of all faults. The above procedures are performed dynamically and a reduced intersection graph is maintained to reduce memory and simulation time. No dictionary or fault simulation is required. Results are provided for all large ISCAS89 benchmark circuits. For the largest benchmark circuit, the procedure reduces the space of all bridging faults, which is of the order of 10^9 to a few hundred faults on the average in about 30 seconds of execution time.