Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Rectification of multiple logic design errors in multiple output circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Logic synthesis for engineering change
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Design verification via simulation and automatic test pattern generation
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Diagnosis and correction of multiple logic design errors in digital circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A deductive technique for diagnosis of bridging faults
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Error Tracer: A Fault-Simualtion-Based Approach to Design Error Diagnosis
Proceedings of the IEEE International Test Conference
Dynamic diagnosis of sequential circuits based on stuck-at faults
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
On error correction in macro-based circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On correction of multiple design errors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automatic Error Correction of Large Circuits Using Boolean Decomposition and Abstraction
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
On Efficient Error Diagnosis of Digital Circuits
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Accurate rank ordering of error candidates for efficient HDL design debugging
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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With the increase in the complexity of VLSI circuit design, logic design errors can occur during synthesis. In this work, we present a method for multiple design error diagnosis and correction. Our approach uses the results of test vector simulation for both error detection and error correction. This makes it applicable to circuits with no global BDD representation. In addition, diagnosis is performed through an implicit enumeration of potentially erroneous lines in an effort to avoid the exponential explosion of the error space. Experimental results on ISCAS'85 benchmark circuits show that our approach can typically detect and correct 1, 2 and 3 errors within seconds of CPU time.