Diagnosis and correction of logic design errors in digital circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Logic synthesis for engineering change
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
An experimental evaluation of selective mutation
ICSE '93 Proceedings of the 15th international conference on Software Engineering
RT-Level ITC'99 Benchmarks and First ATPG Results
IEEE Design & Test
Error Tracer: A Fault-Simualtion-Based Approach to Design Error Diagnosis
Proceedings of the IEEE International Test Conference
Towards an automatic diagnosis for high-level design validation
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Modeling the unknown! Towards model-independent fault and error diagnosis
ITC '98 Proceedings of the 1998 IEEE International Test Conference
On efficient error diagnosis of digital circuits
Proceedings of the IEEE International Test Conference 2001
Advanced techniques for RTL debugging
Proceedings of the 40th annual Design Automation Conference
Effective Error Diagnosis for RTL Designs in HDLs
ATS '02 Proceedings of the 11th Asian Test Symposium
Hierarchical Error Diagnosis Targeting RTL Circuits
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Error Diagnosis of Sequential Circuits Using Region-Based Model
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
Multiple Design Error Diagnosis and Correction in Digital VLSI Circuits
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Efficient Design Error Correction of Digital Circuits
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Automated Source-Level Error Localization in Hardware Designs
IEEE Design & Test
ErrorTracer: design error diagnosis based on fault simulation techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
OCCOM-efficient computation of observability-based code coverage metrics for functional verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fault diagnosis and logic debugging using Boolean satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A New Algorithm for VHDL Parallel Simulation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automated design debugging in a testbench-based verification environment
Microprocessors & Microsystems
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When hardware description languages (HDLs) are used in describing the behavior of a digital circuit, design errors (or bugs) almost inevitably appear in the HDL code of the circuit. Existing approaches attempt to reduce efforts involved in this debugging process by extracting a reduced set of error candidates. However, the derived set can still contain many error candidates, and finding true design errors among the candidates in the set may still consume much valuable time. A debugging priority method [21] was proposed to speed up the error-searching process in the derived error candidate set. The idea is to display error candidates in an order that corresponds to an individual's degree of suspicion. With this method, error candidates are placed in a rank order based on their probability of being an error. The more likely an error candidate is a design error (or a bug), the higher the rank order that it has. With the displayed rank order, circuit designers should find design errors quicker than with blind searching when searching for design errors among all the derived candidates. However, the currently used confidence score (CS) for deriving the debugging priority has some flaws in estimating the likelihood of correctness of error candidates due to the masking error situation. This reduces the degree of accuracy in establishing a debugging priority. Therefore, the objective of this work is to develop a new probabilistic confidence score (PCS) that takes the masking error situation into consideration in order to provide a more reliable and accurate debugging priority. The experimental results show that our proposed PCS achieves better results in estimating the likelihood of correctness and can indeed suggest a debugging priority with better accuracy, as compared to the CS.