Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
The Transduction Method-Design of Logic Networks Based on Permissible Functions
IEEE Transactions on Computers
Verification of synchronous sequential machines based on symbolic execution
Proceedings of the international workshop on Automatic verification methods for finite state systems
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A resynthesis approach for network optimization
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Diagnosis and correction of logic design errors in digital circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
Perturb and simplify: multi-level boolean network optimizer
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Heuristic minimization of BDDs using don't cares
DAC '94 Proceedings of the 31st annual Design Automation Conference
Incremental logic synthesis through gate logic structure identification
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Incremental Synthesis for Engineering Changes
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Error correction based on verification techniques
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Engineering change in a non-deterministic FSM setting
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Fault-simulation based design error diagnosis for sequential circuits
DAC '98 Proceedings of the 35th annual Design Automation Conference
A boolean satisfiability-based incremental rerouting approach with application to FPGAs
Proceedings of the conference on Design, automation and test in Europe
Design Error Diagnosis with Re-Synthesis in Combinational Circuits
Journal of Electronic Testing: Theory and Applications
ATPG-based logic synthesis: an overview
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Incremental logic rectification
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Simulation-Based Design Error Diagnosis and Correction in Combinational Digital Circuits
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Multiple Design Error Diagnosis and Correction in Digital VLSI Circuits
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
ErrorTracer: A Fault Simulation-Based Approach to Design Erorr Diagnosis
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Incremental Design Debugging in a Logic Synthesis Environment
Journal of Electronic Testing: Theory and Applications
On the relation between simulation-based and SAT-based diagnosis
Proceedings of the conference on Design, automation and test in Europe: Proceedings
From Error to Error: Logic Debugging in the Many-Core Era
Electronic Notes in Theoretical Computer Science (ENTCS)
Using unsatisfiable cores to debug multiple design errors
Proceedings of the 18th ACM Great Lakes symposium on VLSI
New spare cell design for IR drop minimization in Engineering Change Order
Proceedings of the 46th Annual Design Automation Conference
Accurate rank ordering of error candidates for efficient HDL design debugging
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the Conference on Design, Automation and Test in Europe
Integration, the VLSI Journal
Reconfigurable ECO cells for timing closure and IR drop minimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A robust functional ECO engine by SAT proof minimization and interpolation techniques
Proceedings of the International Conference on Computer-Aided Design
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