Logic synthesis for engineering change
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Error correction based on verification techniques
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A Fast Algorithm for Locating and Correcting Simple Design Errors in VLSI Digital Circuits
GLS '97 Proceedings of the 7th Great Lakes Symposium on VLSI
Efficient Design Error Correction of Digital Circuits
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Fixing Design Errors with Counterexamples and Resynthesis
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Scalable exploration of functional dependency by interpolation and incremental SAT solving
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Towards automated ECOs in FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Interpolant generation without constructing resolution graph
Proceedings of the 2009 International Conference on Computer-Aided Design
DeltaSyn: an efficient logic difference optimizer for ECO synthesis
Proceedings of the 2009 International Conference on Computer-Aided Design
Design error diagnosis and correction via test vector simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Interpolation-based incremental ECO synthesis for multi-error logic rectification
Proceedings of the 48th Design Automation Conference
Match and replace: a functional ECO engine for multi-error circuit rectification
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the International Conference on Computer-Aided Design
Intuitive ECO synthesis for high performance circuits
Proceedings of the Conference on Design, Automation and Test in Europe
A counterexample-guided interpolant generation algorithm for SAT-based model checking
Proceedings of the 50th Annual Design Automation Conference
Multi-patch generation for multi-error logic rectification by interpolation with cofactor reduction
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Functional rectification in late design stages has been a crucial process in modern complex system design. This paper proposes a robust functional ECO engine, which applies SAT proof minimization and interpolation techniques to automate patch construction to make old implementation and golden specification functionally equivalent. The SAT proof minimization technique provides a sound and efficient way of fixing easy errors, and the interpolation technique provides a complete and robust way of fixing remaining errors. Experimental results show that our engine performs robustly to generate small patches in fixing various design rectification instances.