Design rewiring based on diagnosis techniques
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Design Verification by Test Vectors and Arithmetic Transform Universal Test Set
IEEE Transactions on Computers
Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Diagnosing multiple transition faults in the absence of timing information
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Incremental Design Debugging in a Logic Synthesis Environment
Journal of Electronic Testing: Theory and Applications
Logic verification based on diagnosis techniques
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
An automatic interconnection rectification technique for SoC design integration
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
On the relation between simulation-based and SAT-based diagnosis
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Theory of wire addition and removal in combinational Boolean networks
Microelectronic Engineering
Automating post-silicon debugging and repair
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Using unsatisfiable cores to debug multiple design errors
Proceedings of the 18th ACM Great Lakes symposium on VLSI
The day Sherlock Holmes decided to do EDA
Proceedings of the 46th Annual Design Automation Conference
Debugging strategies for mere mortals
Proceedings of the 46th Annual Design Automation Conference
Fast detection of node mergers using logic implications
Proceedings of the 2009 International Conference on Computer-Aided Design
Automatic fault localization for property checking
HVC'06 Proceedings of the 2nd international Haifa verification conference on Hardware and software, verification and testing
Proceedings of the Conference on Design, Automation and Test in Europe
Integration, the VLSI Journal
Automated design debugging with maximum satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
From RTL to silicon: the case for automated debug
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Managing complexity in design debugging with sequential abstraction and refinement
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Extraction error modeling and automated model debugging in high-performance custom designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Interpolation-based incremental ECO synthesis for multi-error logic rectification
Proceedings of the 48th Design Automation Conference
A robust functional ECO engine by SAT proof minimization and interpolation techniques
Proceedings of the International Conference on Computer-Aided Design
Automated design debugging in a testbench-based verification environment
Microprocessors & Microsystems
Multi-patch generation for multi-error logic rectification by interpolation with cofactor reduction
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Microprocessors & Microsystems
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With the increase in the complexity of digital VLSI circuit design, logic design errors can occur during synthesis. In this paper, we present a test vector simulation-based approach for multiple design error diagnosis and correction. Diagnosis is performed through an implicit enumeration of the erroneous lines in an effort to avoid the exponential explosion of the error space as the number of errors increases. Resynthesis during correction is as little as possible so that most of the engineering effort invested in the design is preserved. Since both steps are based on test vector simulation, the proposed approach is applicable to circuits with no global binary decision diagram representation. Experiments on ISCAS'85 benchmark circuits exhibit the robustness and error resolution of the proposed methodology. Experiments also indicate that test vector simulation is indeed an attractive technique for multiple design error diagnosis and correction in digital VLSI circuits