Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Rectification of multiple logic design errors in multiple output circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Diagnosis and correction of multiple logic design errors in digital circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Formal Equivalence Checking and Design DeBugging
Formal Equivalence Checking and Design DeBugging
Modeling the unknown! Towards model-independent fault and error diagnosis
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Writing Testbenches: Functional Verification of HDL Models, Second Edition
Writing Testbenches: Functional Verification of HDL Models, Second Edition
Advanced Formal Verification
Post-verification debugging of hierarchical designs
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Abstraction and refinement techniques in automated design debugging
Proceedings of the conference on Design, automation and test in Europe
On resolution proofs for combinational equivalence
Proceedings of the 44th annual Design Automation Conference
Trace Compaction using SAT-based Reachability Analysis
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Automating post-silicon debugging and repair
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Design error diagnosis and correction via test vector simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fault diagnosis and logic debugging using Boolean satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Simulation-Based Bug Trace Minimization With BMC-Based Refinement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automatic Fault Localization for Property Checking
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Semiconductor design companies are in a continuous search for design tools that address the ever increasing chip design complexity coupled with strict time-to-market schedules and budgetary constraints. A fundamental aspect of the design process that remains primitive is that of debugging. It takes months to close, it introduces costs and it may jeopardize the release date of the chip. This paper reviews the debugging problem and the research behind it over the past 20 years. The case for automated RTL debug tools and methodologies is also made to help ease the manual burden and complement current industrial verification practices.