Verification of large synthesized designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
HANNIBAL: an efficient tool for logic verification based on recursive learning
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Equivalence checking using cuts and heaps
DAC '97 Proceedings of the 34th annual Design Automation Conference
A Computing Procedure for Quantification Theory
Journal of the ACM (JACM)
A machine program for theorem-proving
Communications of the ACM
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Verification of Proofs of Unsatisfiability for CNF Formulas
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
DAG-aware circuit compression for formal verification
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Dynamic transition relation simplification for bounded property checking
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
DAG-aware AIG rewriting a fresh look at combinational logic synthesis
Proceedings of the 43rd annual Design Automation Conference
Improvements to combinational equivalence checking
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Extended resolution proofs for conjoining BDDs
CSR'06 Proceedings of the First international computer science conference on Theory and Applications
Extended resolution proofs for symbolic SAT solving with quantification
SAT'06 Proceedings of the 9th international conference on Theory and Applications of Satisfiability Testing
Robust Boolean reasoning for equivalence checking and functional property verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
The day Sherlock Holmes decided to do EDA
Proceedings of the 46th Annual Design Automation Conference
Combinational techniques for sequential equivalence checking
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
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Modern combinational equivalence checking (CEC) engines are complicated programs which are difficult to verify. In this paper we show how a modern CEC engine can be modified to produce a proof of equivalence when it proves a miter unsatisfiable. If the CEC engine formulates the problem as a single SAT instance (call this naive), one can use the resolution proof of unsatisfiability as a proof of equivalence. However, a modern CEC engine does not directly invoke a SAT solver for the whole miter, but instead uses a variety of techniques such as structural hashing, detection of intermediate functional equivalences, and circuit re-writing to first simplify the problem. We show that in spite of using these simplification techniques, a CEC engine can be modified to generate a single (extended) resolution proof for the whole miter just as in the naive case. The benefit of having a single proof is that the proof verification program remains extremely simple, and its correctness is much easier to establish than that of the CEC engine.