HANNIBAL: an efficient tool for logic verification based on recursive learning

Multi-level logic optimization by implication analysis

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

Verity—a formal verification program for custom CMOS circuits

IBM Journal of Research and Development - Special issue: IBM CMOS technology

Advanced verification techniques based on learning

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

A single-path-oriented fault-effect propagation in digital circuits considering multiple-path sensitization

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

An efficient equivalence checker for combinational circuits

DAC '96 Proceedings of the 33rd annual Design Automation Conference

Sequential redundancy identification using recursive learning

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design

VERILAT: verification using logic augmentation and transformations

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design

A SAT-based implication engine for efficient ATPG, equivalence checking, and optimization of netlists

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design

A fast sequential learning technique for real circuits with application to enhancing ATPG performance

DAC '98 Proceedings of the 35th annual Design Automation Conference

Verification of RTL generated from scheduled behavior in a high-level synthesis flow

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design

An efficient filter-based approach for combinational verification

DATE '99 Proceedings of the conference on Design, automation and test in Europe

Combinational equivalence checking using satisfiability and recursive learning

DATE '99 Proceedings of the conference on Design, automation and test in Europe

Symbolic model checking using SAT procedures instead of BDDs

Proceedings of the 36th annual ACM/IEEE Design Automation Conference

Novel verification framework combining structural and OBDD methods in a synthesis environment

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

AQUILA: An Equivalence Checking System for Large Sequential Designs

IEEE Transactions on Computers

An Efficient Logic Equivalence Checker for Industrial Circuits

Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification

Power optimization of technology-dependent circuits based on symbolic computation of logic implications

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Using SAT for combinational equivalence checking

Proceedings of the conference on Design, automation and test in Europe

Automatic partitioning for efficient combinatorial verification

ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference

Combinational and sequential equivalence checking

Logic Synthesis and Verification

Verification of integer multipliers on the arithmetic bit level

Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design

Efficient Combinational Verification Using Overlapping Local BDDs and a Hash Table

Formal Methods in System Design

Verifying the correctness of FPGA logic synthesis algorithms

FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays

Design Verification of FPGA Implementations

IEEE Design & Test

Applied Boolean Equivalence Verification and RTL Static Sign-Off

IEEE Design & Test

SAT and ATPG: Boolean engines for formal hardware verification

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

VERIFUL: VERIfication using FUnctional Learning

EDTC '95 Proceedings of the 1995 European conference on Design and Test

Formal Verification of Combinational Circuit

VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications

An effective and efficient ATPG-based combinational equivalence checker

GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI

Dynamic transition relation simplification for bounded property checking

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design

Enhancing SAT-based equivalence checking with static logic implications

HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop

Logic verification based on diagnosis techniques

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference

SAT sweeping with local observability don't-cares

Proceedings of the 43rd annual Design Automation Conference

On resolution proofs for combinational equivalence

Proceedings of the 44th annual Design Automation Conference

Merging nodes under sequential observability

Proceedings of the 45th annual Design Automation Conference

A BDD-based verification method for large synthesized circuits

Integration, the VLSI Journal

Finding Multiple Equivalence-Preserving Transformations in Combinational Circuits through Incremental-SAT

Journal of Electronic Testing: Theory and Applications

Automatic test pattern generation

SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems