VERIFUL: VERIfication using FUnctional Learning

Authors:
R. Mukherjee;J. Jain;M. Fujita
Affiliations:
Fujitsu Laboratories of America, 77 Rio Robles, San Jose CA;Fujitsu Laboratories of America, 77 Rio Robles, San Jose, CA;Fujitsu Laboratories of America, 77 Rio Robles, San Jose, CA
Venue:
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Year:
1995

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Abstract

It is well known that learning (i.e., indirect implications) based techniques perform very well in many instances of combinational circuit verification when the two circuits being verified have many corresponding internal equivalent points. We present some results on combinational circuit design verification using a powerful, and highly general learning technique called functional learning. Functional learning is based on OBDDs and hence can efficiently learn novel implications based on functional manipulation.