A topological search algorithm for ATPG
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Perturb and simplify: multi-level boolean network optimizer
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Multi-level logic optimization by implication analysis
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Code generation and analysis for the functional verification of micro processors
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Test Generation for Ultra-Large Circuits Using ATPG Constraints and Test-Pattern Templates
Proceedings of the IEEE International Test Conference on Test and Design Validity
ITC '98 Proceedings of the 1998 IEEE International Test Conference
ATPG in practical and non-traditional applications
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Extracting gate-level networks from simulation tables
ITC '98 Proceedings of the 1998 IEEE International Test Conference
An ATPG-Based Framework for Verifying Sequential Equivalence
Proceedings of the IEEE International Test Conference on Test and Design Validity
VERIFUL: VERIfication using FUnctional Learning
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Testing "untestable" faults in three-state circuits
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Using ATPG for clock rules checking in complex scan designs
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Switch-level modeling of transistor-level stuck-at faults
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Using Verilog Simulation Libraries for ATPG
ITC '99 Proceedings of the 1999 IEEE International Test Conference
On the Acceleration of Test Generation Algorithms
IEEE Transactions on Computers
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Design and test tools, such as automatic test-pattern generators(ATPG) and fault-simulators, work on a "flattened"simulation model of the entire design. Run-time performanceis directly influenced by the number and complexityof simulation primitives in the flattened model. Moreover,the memory required to flatten and store the simulationmodel of current multi-million-gate designs may exceed theavailable address space of 32-bit computers. We presentseveral model-optimization techniques that significantlyreduce the number of simulation primitives and the associatedmemory usage while still preserving a complete, highlyefficient flattened model. A commercial ATPG productimplementing these techniques demonstrates fast simulationmodel construction for very large designs using a relativelysmall memory space.