Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
AVPGEN—a test generator for architecture verification
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Digital Technical Journal - Special 10th anniversary issue
The SPLASH-2 programs: characterization and methodological considerations
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Designing and Building Parallel Programs: Concepts and Tools for Parallel Software Engineering
Designing and Building Parallel Programs: Concepts and Tools for Parallel Software Engineering
Multiprocessor validation of the Pentium Pro microprocessor
COMPCON '96 Proceedings of the 41st IEEE International Computer Conference
Design Verification of a Super-Scalar RISC Processor
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
A C-based RTL design verification methodology for complex microprocessor
DAC '97 Proceedings of the 34th annual Design Automation Conference
Hierarchical random simulation approach for the verification of S/390 CMOS multiprocessors
DAC '97 Proceedings of the 34th annual Design Automation Conference
DAC '97 Proceedings of the 34th annual Design Automation Conference
User defined coverage—a tool supported methodology for design verification
DAC '98 Proceedings of the 35th annual Design Automation Conference
High-level design verification of microprocessors via error modeling
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Micro architecture coverage directed generation of test programs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
High-level test generation for design verification of pipelined microprocessors
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Verification of configurable processor cores
Proceedings of the 37th Annual Design Automation Conference
Pre-silicon verification of the Alpha 21364 microprocessor error handling system
Proceedings of the 38th annual Design Automation Conference
Design experience of a chip multiprocessor merlot and expectation to functional verification
Proceedings of the 15th international symposium on System Synthesis
Postsilicon Validation Methodology for Microprocessors
IEEE Design & Test
Using ATPG for clock rules checking in complex scan designs
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
OPTIMIZING THE FLATTENED TEST-GENERATION MODEL FOR VERY LARGE DESIGNS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Probabilistic regression suites for functional verification
Proceedings of the 41st annual Design Automation Conference
A probabilistic alternative to regression suites
Theoretical Computer Science
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