Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Fault-Tolerant Features in the HaL Memory Management Unit
IEEE Transactions on Computers - Special issue on fault-tolerant computing
HALSIM - A Very Fast SPARC-V9 Behavioral Model
MASCOTS '95 Proceedings of the 3rd International Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems
Architectural overview of HaL systems
COMPCON '95 Proceedings of the 40th IEEE Computer Society International Conference
Code generation and analysis for the functional verification of micro processors
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A BNF-based automatic test program generator for compatible microprocessor verification
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Assertion-based verification of a 32 thread SPARC™ CMT microprocessor
Proceedings of the 45th annual Design Automation Conference
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This paper provides an overview of the design verification methodology for HaL's Sparc64 processor development. This activity covered approximately two and half years of design development time. Objectives and challenges are discussed and the verification methodology is described. Monitoring mechanisms that give high observability to internal design states, novel features that increase the simulation speed, and tools for automatic result checking are described. Also presented in this paper, for the first time, is an analysis of the design defects discovered during the verification process. Such an analysis is useful in augmenting verification programs to target common design defects.