Assertion-based verification turns the corner
IEEE Design & Test
Design Verification of a Super-Scalar RISC Processor
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
Proceedings of the 42nd annual Design Automation Conference
Hybrid Approach to Faster Functional Verification with Full Visibility
IEEE Design & Test
Applied Assertion-Based Verification: An Industry Perspective
Foundations and Trends in Electronic Design Automation
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Exhaustive property checking, design defect isolation and functional coverage measurement are some of the key challenges of design verification. This paper describes how an assertion based approach successfully addressed these challenges for the verification of an enterprise class chip-multi-threaded (CMT) SPARC™ microprocessor. Methodology and experiences are discussed and recommendations are made on how to incorporate this into the design verification process. Experience with using assertion checks for formal verification as well as simulation based verification is presented, which is part of over 100 person year design verification effort.