Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Error Control Coding, Second Edition
Error Control Coding, Second Edition
On the Yield of VLSI Processors with On-Chip CPU Cache
IEEE Transactions on Computers
Guest Editors' Introduction: Online VLSI Testing
IEEE Design & Test
Error Detection and Handling in a Superscalar, Speculative Out-of-Order Execution Processor System
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
Design Verification of a Super-Scalar RISC Processor
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
Mitigating Soft Errors in Highly Associative Cache with CAM-based Tag
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
A cache-defect-aware code placement algorithm for improving the performance of processors
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
An error tolerant CAM with nand match-line organization
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
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This paper describes fault-tolerant and error detection features in HaL's memory management unit (MMU). The proposed fault-tolerant features allow recovery from transient errors in the MMU. It is shown that these features were natural choices considering the architectural and implementation constraints in the MMU's design environment. Three concurrent error detection and correction methods employed in address translation and coherence tables in the MMU are described. Virtually-indexed and virtually-tagged cache architecture is exploited to provide an almost fault-secure hardware coherence mechanism in the MMU, with very small performance overhead (less than 0.01% in the instruction throughput). Low overhead linear polynomial codes have been chosen in these designs to minimize both the hardware and software instrumentation impact.Index Terms驴Coherence, concurrent error detection/ correction, linear polynomial codes, translation lookaside buffers, content addressable memory, memory management unit, fault-tolerant computing.