Fault-Tolerant Features in the HaL Memory Management Unit
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Space/time trade-offs in hash coding with allowable errors
Communications of the ACM
An adaptive serial-parallel CAM architecture for low-power cache blocks
Proceedings of the 2002 international symposium on Low power electronics and design
Cache Scrubbing in Microprocessors: Myth or Necessity?
PRDC '04 Proceedings of the 10th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC'04)
Mitigating Soft Errors in Highly Associative Cache with CAM-based Tag
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Error-Correcting Codes for Ternary Content Addressable Memories
IEEE Transactions on Computers
Hybrid-type CAM design for both power and performance efficiency
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
PEDS: a parallel error detection scheme for TCAM devices
IEEE/ACM Transactions on Networking (TON)
Low-power high-performance NAND match line content addressable memories
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Cost Effective Protection Techniques for TCAM Memory Arrays
IEEE Transactions on Computers
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Content Addressable Memories (CAMs) are valuable components in applications where fast, highly-associative searches are required. While common SRAMs can be protected from soft-errors using error-correcting codes (ECC), CAMs are much harder to protect against such effects. The main problem is that the comparison of a stored memory word to a search word, when both are encoded by ECCs, is far too complicated and expensive to be performed directly by circuits at each row of the CAM. The proposed design uses a modified NAND-type, dual match-line organization which keeps track of up to 1 bit mismatch per row. As CAM words are encoded using an ECC of Hamming distance of 3, a single bit error can be "corrected" during the search operation, by ignoring any single-bit mismatch. The design is analyzed in detail with regard to charge-sharing noise, speed and power and the cost of error-tolerance is investigated against a state-of-the art NAND-type CAM. Compared against the best-known, error-tolerant CAM, which uses a NOR match-line organization, the proposed circuit is faster and more energy efficient.