Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor
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SWIFT: Software Implemented Fault Tolerance
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Soft error benchmarking of L2 caches with PARMA
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Soft error benchmarking of L2 caches with PARMA
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Setting an error detection infrastructure with low cost acoustic wave detectors
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A study of DRAM failures in the field
SC '12 Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis
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SC '13 Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis
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Journal of Network and Systems Management
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Transient faults from neutron and alpha particle strikes in large SRAM caches have become a major problem for microprocessor designers. To protect these caches, designers often use error correcting codes (ECC), which typically provide single-bit error correction and double-bit error detection (SECDED). Unfortunately, two separate strikes could still flip two different bits in the same ECC-protected word. This we call a temporal double-bit error. SECDED ECC can only detect 驴 not correct 驴 such errors.This paper shows how to compute the mean time to failure for temporal double-bit errors. Additionally, we show how fixed-interval scrubbing 驴 in which error checkers periodically access cache blocks and remove single-bit errors 驴 can mitigate such errors in processor caches. Our analysis using current soft error rates shows that only very large caches (e.g., hundreds of megabytes to gigabytes) need scrubbing to reduce the temporal double-bit error rate to a tolerable range.