Optimizing power and performance for reliable on-chip networks

Authors:
Aditya Yanamandra;Soumya Eachempati;Niranjan Soundararajan;Vijaykrishnan Narayanan;Mary Jane Irwin;Ramakrishnan Krishnan
Affiliations:
The Pennsylvania State University;The Pennsylvania State University;The Pennsylvania State University;The Pennsylvania State University;The Pennsylvania State University;The Pennsylvania State University
Venue:
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Year:
2010

Citing 14
Cited 3

Simics: A Full System Simulation Platform

Computer
Low Power Error Resilient Encoding for On-Chip Data Buses

Proceedings of the conference on Design, automation and test in Europe
Power-driven Design of Router Microarchitectures in On-chip Networks

Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Cache Scrubbing in Microprocessors: Myth or Necessity?

PRDC '04 Proceedings of the 10th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC'04)
CMOS Electronics: How It Works, How It Fails

CMOS Electronics: How It Works, How It Fails
Principles and Practices of Interconnection Networks

Principles and Practices of Interconnection Networks
Adapative Error Protection for Energy Efficiency

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Analysis of Error Recovery Schemes for Networks on Chips

IEEE Design & Test
Exploring Fault-Tolerant Network-on-Chip Architectures

DSN '06 Proceedings of the International Conference on Dependable Systems and Networks
iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures

ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
A Lightweight Fault-Tolerant Mechanism for Network-on-Chip

NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Impact of Process and Temperature Variations on Network-on-Chip Design Exploration

NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Measuring Architectural Vulnerability Factors

IEEE Micro
The PARSEC benchmark suite: characterization and architectural implications

Proceedings of the 17th international conference on Parallel architectures and compilation techniques

RAFT: A router architecture with frequency tuning for on-chip networks

Journal of Parallel and Distributed Computing
Exploiting inherent information redundancy to manage transient errors in NoC routing arbitration

NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Addressing network-on-chip router transient errors with inherent information redundancy

ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Wireless Health Systems, On-Chip and Off-Chip Network Architectures

Quantified Score

Hi-index	0.00

Visualization

Abstract

We propose novel techniques to minimize the power and performance penalties in protecting the NoC against soft errors, while giving desired reliability guarantees. Some applications have inherent error tolerance which can be exploited to save power, by turning off the error correction mechanisms for a fraction of the total time without trading off reliability. To further increase the power savings, we bound the vulnerability of a router by throttling the traffic into the router. In order to minimize the throughput loss due to throttling, we propose dividing the die into domains and using multiple vulnerability bounds across these domains. We explore both static and dynamic selection of vulnerability bounds. We find that for applications with an error tolerance of 10% of the raw error rate, the dynamic multiple vulnerability bound scheme can save up to 44% of power expended for error correction at a marginal network throughput loss of 3%.